Faraday 0.11µm libraries and IP are developed for UMC L110E processes. The library enables users to achieve their design goals with ultimate speed, power, and density especially when it is used in conjunction with our most up-to-date synthesis tools. In order to improve wafer yield and reduce cost for our clients, Faraday 0.11µm libraries have been carefully tested and verified in silicon to ensure the highest degree of manufacturing success.

Please check features listed below:

   
 
UMC 0.11µm Process
  UMC L110 High Speed Copper Process
 
   
  UMC L110 Low Leakage Copper Process
 
  • FSR0L_D_Generic_Core
  • FOR0L_A33_T33_Generic_IO
  • FOR0L_A33_50VT_Generic_IO
  • FOR0L_A33_T33_ANALOGESD_IO
  • FOR0L_A33_T33_OSC_HIGH_IO
 
  UMC L110 Standard Performance Copper Process
 
  • FSR0G_D_Generic_Core
  • FOR0G_A33_T33_Generic_IO
  • FOR0G_A33_50VT_Generic_IO
  • FOR0G_A33_T33_ANALOGESD_IO
  • FOR0G_A33_T33_OSC_HIGH_IO
 
  UMC L110 High Speed Aluminum Process
 
 

 

UMC L110 High Speed Copper Process
  FSR0H_D_Generic_Core
 
  • UMC's 0.11 μm 1P8M FSG logic process
  • Raw gate density: 300k gates/mm2 offers high density needed for low cost applications
  • A wide range of drive strengths and optimized P/N ratio for superior performance
  • A complete set of models for industry-standard EDA tools
  • A full set of gated clock buffers for power saving
  • Each cell has at least one sub/well contact
  • Flexible row abutment
  • Built-in decoupling capacitance to aid IR drop in filler cells
  • 1.2 V ± 10 % characterization range
  • Optional 1.0 V ± 10 % characterization range
  • View Details
 
  FOR0H_A33_T33_Generic_IO
 
  • UMC 0.11 μm logic HS (FSG) process
  • 3.3 V input and 3.3 V output drive
  • Output buffer with the programmable drive strengths from 2 mA to 8 mA in steps of 2 mA, and from 4 mA to 16 mA in steps of 4 mA
  • Input buffer with the programmable features of pull-up/pull-down resistance, keeper, and Schmitt-trigger
  • Built-in antenna diodes for all the pins
  • ESD robustness and latch-up immunity proven by silicon
  • View Details
 
  FOR0H_A33_50VT_Generic_IO
 
  • UMC 0.11 μm logic HS (FSG) process
  • 3.3 V with 5 V tolerance input
  • 3.3 V output drive
  • Output buffer with the programmable drive strengths from 2 mA to 8 mA in step of 2 mA, and from 4 mA to 16 mA in steps of 4 mA
  • Input buffer with the programmable features of pull-up/pull-down resistances, keeper, and Schmitt-trigger
  • Built-in antenna diodes for all pins
  • ESD robustness and latch-up immunity proven by silicon
  • View Details
 
  FSR0H_D_SH (1Port SRAM)
 
  • Synchronous read and write operations
  • Full customized layout density per customers’ configurations
  • High density, available in 1.2 V ± 10%
  • Automatic power down to eliminate the DC current
  • Clocked address inputs and CS to the RAM at the CK rising edge
  • Clocked web input pins to the RAM at the CK rising edge
  • Clocked DI input pins to the RAM at the CK rising edge
  • Byte/Word write operations available
  • Verilog/VHDL timing/simulation model generators
  • SPICE netlist generator
  • GDSII layout generator
  • Memaker preview UI
  • Supports the BIST codes
  • Multi-block options for the best aspect ratio
  • View Details
 
  FSR0H_D_SJ (Dual Port SRAM)
 
  • Synchronous read and write operations
  • Low leakage device-based design
  • Fully customized layout density
  • Available at 1.2 V ± 10%
  • Automatic power-down mechanism to eliminate the DC current
  • Clocked address inputs and CSA(B) to RAM with the CKA(B) rising edge
  • Clocked WEA(B)N input pins to RAM with the CKA(B) rising edge
  • Clocked DIA(B) input pins to RAM with the CKA(B) rising edge
  • Byte write and word write operations available
  • Verilog/VHDL timing/simulation model generator
  • SPICE netlist generator
  • GDSII layout database
  • Memaker preview user interface
  • Supports BIST code
  • Column Mux options for the best aspect ratio
  • View Details
 
  FSR0H_D_SY (1 Port Register File)
 
  • Synchronous read and write operations
  • Fully customized layout density
  • 1.2 V ± 10% operating voltage available
  • Automatic power down to eliminate the DC current
  • Clocked address inputs and CSB to the RAM at the CK rising edge
  • Clocked weband DI input pins to the RAM at the CK rising edge
  • Byte write and word write operations available
  • Verilog/VHDL timing/simulation model generators
  • SPICE netlist generator
  • GDSII layout database
  • Memaker preview UI
  • Supports the BIST codes
  • Column Mux options for the best aspect ratio
  • View Details
 
  FSR0H_D_SZ (2 Port Register File)
 
  • Synchronous read and write operations
  • Fully customized layout density
  • Available in 1.2 V ± 10%
  • Automatic power down to eliminate the DC current
  • Clocked address inputs and CSA(B)N to RAM at the CKA(B) rising edge
  • Clocked WEB input pins to RAM at the CKB rising edge
  • Clocked DI input pins to RAM at the CKB rising edge
  • Byte write or word write operations available
  • Verilog/VHDL timing simulation model generators
  • SPICE netlist generator
  • GDSII layout database
  • Memaker preview UI
  • Column mux options for the best aspect ratio
  • View Details
 
  FSR0H_D_SP (VIA ROM)
 
  • Synchronous read operation
  • Fully customized layout density per customer's configurations
  • Programmable Via1 code
  • High density available in 1.2 V ±10%
  • Automatic power down to eliminate the DC current
  • Clocked address inputs and CS to the ROM at the CK rising edge
  • Verilog/VHDL timing simulation model generators
  • SPICE netlist generator
  • GDSII layout database
  • Memaker preview UI
  • Supports the BIST code
  • Multi-block options for the best aspect ratio
  • Minimum metal requirement: 5 metal layers
  • View Details
 
UMC L110 High Speed Aluminum Process
  FSR0D_D_Generic_Core
 
  • UMC 0.11 μm logic HS/AL process
  • Raw gate density: 300k gates/mm2 targeting for low-cost applications
  • Provides a wide range of drive strengths and optimized P/N ratios for superior performance
  • Includes a complete set of models for industry-standard EDA tools
  • Supports a full set of gated clock buffers for power saving
  • Each cell has at least one sub/well contact
  • Supports flexible row abutment
  • Built-in decoupling capacitance to reduce IR drop in filler cells
  • Characterization range: 1.2 V ± 10%
  • View Details