UMC Free Library - 0.11 µm IPs

Faraday 0.11µm libraries and IP are developed for UMC L110E processes. The library enables users to achieve their design goals with ultimate speed, power, and density especially when it is used in conjunction with our most up-to-date synthesis tools. In order to improve wafer yield and reduce cost for our clients, Faraday 0.11µm libraries have been carefully tested and verified in silicon to ensure the highest degree of manufacturing success.

Please check features listed below:

	UMC 0.11µm Process
	UMC L110 High Speed Process
	FSR0H_D_Generic_Core FOR0H_A33_T33_Generic_IO FOR0H_A33_50VT_Generic_IO FSR0H_D_SH (1Port SRAM) FSR0H_D_SJ (Dual Port SRAM) FSR0H_D_SY (1 Port Register File) FSR0H_D_SZ (2 Port Register File) FSR0H_D_SP (VIA ROM)

	UMC L110 Low Leakage Process
	FSR0L_D_Generic_Core FOR0L_A33_T33_Generic_IO FOR0L_A33_50VT_Generic_IO FOR0L_A33_T33_ANALOGESD_IO FOR0L_A33_T33_OSC_HIGH_IO

	UMC L110 Standard Performance Process
	FSR0G_D_Generic_Core FOR0G_A33_T33_Generic_IO FOR0G_A33_50VT_Generic_IO FOR0G_A33_T33_ANALOGESD_IO FOR0G_A33_T33_OSC_HIGH_IO

	UMC L110 High Speed Process
	FSR0H_D_Generic_Core
	UMC's 0.11 μm 1P8M FSG logic process Raw gate density: 300k gates/mm2 offers high density needed for low cost applications A wide range of drive strengths and optimized P/N ratio for superior performance A complete set of models for industry-standard EDA tools A full set of gated clock buffers for power saving Each cell has at least one sub/well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells 1.2 V ± 10 % characterization range Optional 1.0 V ± 10 % characterization range View Details

	FSR0H_D_SH (1Port SRAM)
	Synchronous read and write operations Full customized layout density per customers’ configurations High density, available in 1.2 V ± 10% Automatic power down to eliminate the DC current Clocked address inputs and CS to the RAM at the CK rising edge Clocked web input pins to the RAM at the CK rising edge Clocked DI input pins to the RAM at the CK rising edge Byte/Word write operations available Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout generator Memaker preview UI Supports the BIST codes Multi-block options for the best aspect ratio View Details

	FSR0H_D_SY (1 Port Register File)
	Synchronous read and write operations Fully customized layout density 1.2 V ± 10% operating voltage available Automatic power down to eliminate the DC current Clocked address inputs and CSB to the RAM at the CK rising edge Clocked weband DI input pins to the RAM at the CK rising edge Byte write and word write operations available Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST codes Column Mux options for the best aspect ratio View Details

	FSR0H_D_SZ (2 Port Register File)
	Synchronous read and write operations Fully customized layout density Available in 1.2 V ± 10% Automatic power down to eliminate the DC current Clocked address inputs and CSA(B)N to RAM at the CKA(B) rising edge Clocked WEB input pins to RAM at the CKB rising edge Clocked DI input pins to RAM at the CKB rising edge Byte write or word write operations available Verilog/VHDL timing simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Column mux options for the best aspect ratio View Details