UMC Free Library - 0.13 um IPs

Faraday 0.13µm libraries and IP are developed for UMC L130E processes. The library enables users to achieve their design goals with ultimate speed, power, and density especially when it is used in conjunction with our most up-to-date synthesis tools. In order to improve wafer yield and reduce cost for our clients, Faraday 0.13µm libraries have been carefully tested and verified in silicon to ensure the highest degree of manufacturing success.

Please check features listed below:

	UMC 0.13µm Process
	UMC L130E High Speed FSG Library
	FSC0H_D Generic Core Cells FSC0H_D Generic I/O Cells FSC0H_D_T33_OSC_IO FSC0H_D_T33_PCIX_IO FSC0H_D_TMVH33L25_SSTL2C2WLVTTL_IO FSC0H_D_T33_LVPECL_IO FSC0H_D_T33_ANALOGESD_IO FSC0H_D_SH (1Port SRAM) FSC0H_D_SJ (Dual Port SRAM) FSC0H_D_SY (1 Port Register File) FSC0H_D_SW (2 Port Register File) FSC0H_D_SP (VIA ROM) FXPLL110HC0H_APGD FXDLL311HC0H FZOTG111HC0H

	UMC L130E Low Leakage FSG Library
	FSC0L_D Generic Core Cells FSC0L_D Generic I/O Cells FSC0L_D_T33_ANALOGESD_IO FSC0L_D_T33_OSC_IO FSC0L_D_SH (1Port SRAM) FSC0L_D_SJ (Dual Port SRAM) FSC0L_D_SY (1 Port Register File) FSC0L_D_SZ (2 Port Register File) FSC0L_D_SP (VIA ROM) FXPLL010HC0L_APGD

	UMC L130E Fusion FSG Library
	FSC0U_D_SH (1Port SRAM) FSC0U_D_SJ (Dual Port SRAM) FSC0U_D_SY (1 Port Register File) FSC0U_D_SW (2 Port Register File) FSC0U_D_SP (VIA ROM) FXPLL010HC0U_APGD Note: Fusion library is the combination of High Speed and Low Leakage libraries.

	UMC L130E Logic Standard Performance Library
	FSC0G_D Generic Core Cells FSC0G_D Generic I/O Cells FSC0G_D_T33_OSC_IO FSC0G_D_T33_ANALOGESD_IO FSC0G_D_SH (1Port SRAM) FSC0G_D_SJ (Dual Port SRAM) FSC0G_D_SY (1 Port Register File) FSC0G_D_SZ (2 Port Register File) FSC0G_D_SP (VIA ROM)

	UMC L130E High-Gain Mixed-Mode FSG Library
	FOC0M_A33_T33_GENERIC_IO FOC0M_A33_50VT_GENERIC_IO

	UMC L130 CMOS Image Sensor Process
	FSC0I_A_Generic_Core FOC0I_A_T33_Generic_IO FSC0I_A_SH (1Port SRAM) FSC0I_A _SJ (Dual Port SRAM) FSC0I_A _SY (1 Port Register File) FSC0I_A _SZ (2 Port Register File) FSC0I_A _SP (VIA ROM)

	UMC L130E High Speed FSG Features
	FSC0H_D Generic Core Cells
	UMC's "0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process" Raw gate density: 250,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance. Complete set of models for industry-standard EDA tools. Support arithmetic cells for data-path designs. Full set of gated clock buffers for power saving. Each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FSC0H_D Generic I/O Cells
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSC0H_D_T33_GENERIC_IO UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSC0H_D_50VT_GENERIC_IO

	FSC0H_D_T33_OSC_IO
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process High frequency oscillator pad range: 1MHz ~ 66MHz Low frequency oscillator pad range: 32KHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: (only "High" provided in AIP Free Lib)

	FSC0H_D_T33_PCIX_IO
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process Support PCI33, PCI66, PCIX 133MHz 3.3V input, 3.3V output drive Input buffer with programmable pull up resistance, pull down resistance, Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSC0H_D_TMVH33L25_SSTL2C2WLVTTL_IO
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process 3.3V LVTTL input, 3.3V LVTTL output drive 2.5V SSTL2 input, 2.5V SSTL2 output drive Output buffer with SSTL2 (ClassII) / LVTTL (20mA) driving strength Input buffer with Schmitt trigger in LVTTL mode, power down function in SSTL2 mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSC0H_D_T33_LVPECL_IO
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process 3.3V PECL I/O cells Options for 25 ohms and 50 ohms output buffers 300MHz for differential type drivers and receivers 250MHz for single-ended type driver and receivers Support power down mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSC0H_D_T33_ANALOGESD_IO
	UMC's 0.13μm 1.2V/3.3V HS/FSG/L130E Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by Silicon View Details

	FSC0H_D_SH (1Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40° ~ 125℃ Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Full custom layout density per customer configuration Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout generator Memory compiler preview UI (memaker) BIST code supported Multi-block options for the best aspect ratio View Details

	FSC0H_D_SJ (Dual Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp.range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write or word write operations avilable Memory compiler preview UI (memaker) BIST circuitry supported Multi-block　options for the best aspect ratio View Details

	FSC0H_D_SY (1 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSC0H_D_SW (2 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp.range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEB input pin to RAM at CKB rising edge Clocked DI input pins to RAM at CKB rising edge Byte write or word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSC0H_D_SP (VIA ROM)
	Synchronous read operation Fully customized layout density High density available in 1.2 V ± 10% Automatic power down to eliminate the DC current Minimum metal requirement: 5 metal layers Clocked address inputs and CS to ROM at the CK rising edge Programmable Via1 layer code Verilog/VHDL timing simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports BIST code Multi-block options for the best aspect ratio View Details

	FXPLL110HC0H_APGD
	UMC 0.13μm 1.2V High Speed 1P8M Logic process Operating voltage range: 1.08V~ 1.32V IP's minimum metal requirement: 4 metal layers Included power/ground I/O cells Low jitter output Power-down mode No external component required View Details

	FXDLL311HC0H
	UMC 0.13μm 1.2V 1P8M HS process Operating voltage range: 1.08V ~ 1.32V Operating junction temperature range: -40℃ ~ 125℃ Recommended operating ambient temperature range: 0℃ ~ 85℃ IP's minimum metal requirement: 4 metal layers Pure 1.2V power supply DDR SDRAM controller usage Four channels with 20% DQS delay Low jitter output Power-down mode No external component required View Details

	FZOTG111HC0H
	UMC 0.13μm 1.2V/3.3V 1P8M logic high speed FSG enhancement process Operating voltage range: 1.08V ~ 1.32V Operating junction temperature range: -40℃ ~ 125℃ IP's minimum metal requirement: 4 metal layers (4M) 3.3V power supply (I/O) with 5V tolerance Compliant with USB specification 1.1 Compliant with USB On-The-Go supplement specification 1.0 Built-in pull-up / pull-down resistors Support full speed data transfer rate, 12 Mbps Support low speed data transfer rate, 1.5 Mbps ESD protection > 3kV (HBM) IP's minimum oxide requirement: dual oxide (2G) View Details

	UMC L130E Low Leakage FSG Features
	FSC0L_D Generic Core Cells
	UMC's 0.13μm 1.2V/3.3V LL /FSG/L130E Logic Process Raw gate density: 250,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Support arithmetic cells for data-path designs Full set of gated clock buffers for power saving Each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FSC0L_D Generic I/O Cells
	UMC's 0.13μm 1.2V/3.3V LL /FSG/L130E Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper and, Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSC0L_D_T33_GENERIC_IO UMC's 0.13μm 1.2V/3.3V LL/FSG/L130E Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSC0L_D_50VT_GENERIC_IO

	FSC0L_D_T33_ANALOGESD_IO
	UMC's 0.13μm 1.2V/3.3V LL/FSG/L130E Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details

	FSC0L_D_T33_OSC_IO
	UMC's 0.13μm 1.2V/3.3V LL/FSG/L130E Logic Process High frequency oscillator pad range: 1MHz ~ 66MHz Low frequency oscillator pad range: 32KHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSC0L_D_SH (1Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density per customer configuration Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Multi-block options for the best aspect ratio View Details

	FSC0L_D_SJ (Dual Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read and write operations Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write or word write operations available Memory compiler preview GUI (Memaker) BIST code supported Column MUX options for the View Details

	FSC0L_D_SY (1 Port Register File)
	Operating voltage range: 1.08V ~1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column mux options for the best aspect ratio View Details

	FSC0L_D_SZ (2 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSC0L_D_SP (VIA ROM)
	Targeted for the Bonding over Active Circuitry (BOAC) applications Synchronous read operation Fully customized layout density per customer's configurations Programmable Via1 code High density, available in 1.2 V ± 10% Minimum metal requirement: 5 metal layers Automatic power down to eliminate the DC current Clocked address inputs and CS to ROM at the CK rising edge Verilog/VHDL timing simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST code Multi-block options for the best aspect ratio View Details

	FXPLL010HC0L_APGD
	UMC 0.13μm 1.2V Fusion logic process Operating voltage range : 1.08V~1.32V Output frequency range : 12.5MHz~200MHz 8-bit programmable pre-divider 8-bit programmable loop divider IP's minimum metal requirement : 4 metal layers Power-down mode Built-in test mode Built-in loop filter Built-in ESD protection circuit＞2KV (HBM) Built-in core limited power / ground cel View Details

	UMC L130E Fusion FSG Features
	FSC0U_D_SH (1Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Low leakage device-based design, with HS devices on critical path Fully customized layout density per customer configuration Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Memory compiler preview UI (memaker ) BIST circuitry supported Multi-block options for the best aspect ratio View Details

	FSC0U_D_SJ (Dual Port SRAM)
	Low leakage device-based design with HS device on critical path Operating voltage range: 1.08V ~ 1.32V Operating junction temp.range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read and write operations Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA (B) to RAM with CKA (B) rising edge Clocked WEA (B) N input pins to RAM with CKA (B) rising edge Clocked DIA (B) input pins to RAM with CKA (B) rising edge Byte write and word write operations available Memory compiler preview GUI(Memaker) BIST code supported Column MUX options for the best aspect ratio View Details

	FSC0U_D_SY (1 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp.range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Low leakage device-based design, with HS devices on critical path Fully customized layout density Available for 1.2V ± 10% Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pins to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSC0U_D_SW (2 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp.range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEB input pin to RAM at CKB rising edge Clocked DI input pins to RAM at CKB rising edge Byte write or word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSC0U_D_SP (VIA ROM)
	Synchronous read operation Fully customized layout density High density, available in 1.2 V ± 10% Automatic power down to eliminate the DC current Clocked address inputs and CS to the ROM at the CK rising edge Programmable Via1 layer codes Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST codes Multi-block options for the best aspect ratio View Details

	FXPLL010HC0U_APGD
	UMC 0.13μm 1.2V Fusion logic process Operating voltage range : 1.08V~1.32V Operating junction temperature : -40℃ ~ 125℃ Recommended operating ambient temperature : 0℃ ~ 85℃ Output frequency range : 20~400MHz 8-bit programmable pre-divider 8-bit programmable loop divider IP's minimum metal requirement : 3 metal layers Power-down mode Built-in loop filter View Details

	UMC L130E Logic Standard Performance Library
	FSC0G_D Generic Core Cells
	UMC's 0.13µm 1.2V/3.3V SP/FSG/L130E Logic Process Raw gate density: 250,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Full set of gated clock buffers for power saving Only Metal 1 used in layout, each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR-drop in filler cells View Details

	FSC0G_D Generic I/O Cells
	UMC's 0.13μm 1.2V/3.3V SP/FSG/L130E Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSC0G _D_T33_GENERIC_IO UMC's 0.13μm 1.2V/3.3V P/FSG/L130E Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSC0G _D_50VT_GENERIC_IO

	FSC0G_D_T33_OSC_IO
	UMC's 0.13μm 1.2V/3.3V SP/FSG/L130E Logic Process High frequency oscillator pad range: 1MHz ~ 66MHz Low frequency oscillator pad range: 32KHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: (only "High" provided in AIP Free Lib)

	FSC0G_D_T33_ANALOGESD_IO
	UMC's 0.13μm 1.2V/3.3V SP/FSG/L130E Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details

	FSC0G_D_SH (1Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Full custom layout density per customer configuration Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout generator Memory compiler preview UI (memaker) BIST code supported Multi-block options for the best aspect ratio View Details

	FSC0G_D_SJ (Dual Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write and word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column mux options for the best aspect ratio View Details

	FSC0G_D_SY (1 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generato r GDSII layout database Memory compiler preview UI(Memaker) BIST code supported Column mux options for the best aspect ratio View Details

	FSC0G_D_SZ (2 Port Register File)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSC0G_D_SP (VIA ROM)
	Synchronous read operation Fully customized layout density High density, available in 1.2 V ± 10% Automatic power down to eliminate the DC current Minimum metal requirement: 5 metal layers Clocked address inputs and CS to the ROM at the CK rising edge Programmable Via1 layer codes Verilog/VHDL timing simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST codes Multi-block options for the best aspect ratio View Details

	UMC L130E High-Gain Mixed-Mode FSG Features
	FOC0M_A33_T33_GENERIC_IO
	UMC's 0.13μm Mixed Mode/RFCMOS13 1.2V/3.3V 1P8M MMC/FSG/L130E high gain Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FOC0M_A33_50VT_GENERIC_IO
	UMC's 0.13μm Mixed Mode/RFCMOS13 1.2V/3.3V 1P8M MMC/FSG/L130E high gain Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	UMC L130 CMOS Image Sensor Process
	FSC0I_A_Generic_Core
	UMC 0.13 μm CMOS Image Sensor 1.5 V/3.3 V Process Raw gate density: 150,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Supports arithmetic cells for data-path designs Full set of gated clock buffers for power saving Only Metal 1 is used in layout, each cell has at least one sub/well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FOC0I_A_T33_Generic_IO
	UMC 0.13 μm CMOS Image Sensor 1.5 V/3.3 V Process 3.3 V input, 3.3 V output drive Output buffer with programmable driving strength from 2 mA to 16 mA with 2 mA steps Input buffer with programmable pull-up resistance, pull-down resistance, keeper, and Schmitt trigger Built-in antenna diodes for all pins ESD robustness and latch-up immunity proven by silicon View Details

	FSC0I_A_SH (1Port SRAM)
	Operating voltage range: 1.35 V ~ 1.65 V Operating junction temp. range : -40 °C ~ 125 °C Recommended operating ambient temp. range: 0 °C ~ 85 °C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog / VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSC0I_A _SY (1 Port Register File)
	Operating voltage range: 1.35 V ~ 1.65 V Operating junction temperature range:-40 °C ~ 125 °C Operating ambient temperature range:0 °C ~ 85 °C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power-down mechanism to eliminate DC current Clocked address inputs and CS to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write and word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column Mux options for the best aspect ratio View Details

	FSC0I_A _SZ (2 Port Register File)
	Operating voltage range: 1.35 V ~ 1.65 V Operating junction temperature range: -40 °C ~ 125 °C Recommended operating ambient temperature range: 0 °C ~ 85 °C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write and word write operations available Memory compiler preview UI (Memaker) Column Mux options for the best aspect ratio View Details

	FSC0I_A_SP (VIA ROM)
	Synchronous read operation Fully customized layout density High density available for 1.5 V ± 10% Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at the CK rising edge Programmable Via1 layer codes Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) Supports BIST mode Multi-block options for the best aspect ratio View Details