• FSL0A_C_GENERIC_CORE
• FOL0A_A33_T33_GENERIC_IO
• FOL0A_A33_50VT_GENERIC_IO
• FOL0A_A33_T33_ANALOGESD_IO
• FOL0A_A33_T18_OSC_HIGH_IO
• FSL0A_D_SL (1Port SRAM)
• FSL0A_C_SY (1 Port Register File)
• FSL0A_C_SJ (Dual PortSRAM)
• FSL0A_C_SZ (2 Port Register File)
• FSL0A_D_SP (VIA ROM)

• UMC 0.153 μm logic process
• Raw gate density: 110,000 gates/mm² target for the low-cost applications
• A wide range of drive strengths and optimized P/N ratios for superior performance
• Supports a complete set of models for the industry-standard EDA tools
• Supports a full set of gated clock buffers for saving power
• Only M1 layer is used for layout
• Supports the flexible row abutment
• View Details

• Synchronous read and write operations
• High-density, low power, and a small memory design area
• Fully-customized layout density
• Available at 1.8 V ± 10% and 1.5 V ± 10%
• Automatic power-down mechanism to eliminate the DC current
• Clocked address inputs and CSB to RAM at the CK rising edge
• Clocked DI/WEB input pins to RAM at the CK rising edge
• Both byte write and word write operations available
• Verilog/VHDL timing/simulation model generators
• SPICE netlist generator
• GDSII layout database
• Memaker preview UI
• Supports the BIST code
• Column Mux options for the best aspect ratio
• Minimum metal requirement: 5 metal layers
• View Details

• Operating voltage range: 1.62 V ~ 1.98 V
• Operating junction temperature range: -40 °C ~ 125 °C
• Minimum metal requirement: 4 metal layers
• Synchronous read and write operations
• Fully-customized layout density available at 1.8 V ± 10%
• Automatic power-down mechanism to eliminate the DC current
• Clocked address inputs and CSB to RAM with the CK rising edge
• Clocked WEB input pin to RAM with the CK rising edge
• Clocked DI input pins to RAM with the CK rising edge
• Byte write or word write operations available
• Verilog/VHDL timing/simulation model generator
• SPICE netlist generator
• GDSII layout database
• Memaker preview UI
• Supports the BIST code
• Column Mux options for the best aspect ratio
• View Details

• Synchronous read and write operations
• Fully-customized layout density available at 1.8 V ± 10%
• Automatic power-down mechanism to eliminate the DC current
• Clocked address inputs and CSA(B) to the RAM at the
• CKA(B) rising edge
• Clocked WEA(B)N input pins to the RAM at the CKA(B) rising edge
• Clocked DIA(B) input pins to the RAM at the CKA(B) rising edge
• Supports byte write and word write operations
• Verilog/VHDL timing/simulation model generator
• SPICE netlist generator
• GDSII layout database
• Memaker preview UI
• Supports the BIST code
• Column Mux options for the best aspect ratio
• Minimum metal requirement: 5 metal layers
• View Details

• Operating voltage range: 1.62 V ~ 1.98 V
• Operating junction temperature range: -40 °C ~ 125 °C
• Minimum metal requirement: 4 metal layers
• Synchronous read and write operations
• Fully-customized layout density
• Automatic power-down mechanism to eliminate the DC current
• Clocked address inputs and CSA(B)N to RAM with the CKA(B) rising edge
• Clocked WEB input pins to RAM with the CKB rising edge
• Clocked DI input pins to RAM with the CKB rising edge
• Byte write or word write operations available
• Verilog/VHDL timing/simulation model generator
• SPICE netlist generator
• GDSII layout database
• Memaker preview UI
• Supports the BIST code
• Column Mux options for the best aspect ratio
• View Details

• Synchronous read operation
• Fully-customized layout density available at 1.8 V ± 10%
• Automatic power-down mechanism to eliminate the DC current
• Clocked address inputs and CS to ROM at the CK rising edge
• Minimum metal requirement: 5 metal layers
• Programmable Via1 layer codes
• Verilog/VHDL timing/simulation model generator
• SPICE netlist generator
• GDSII layout database
• Memaker preview UI
• Supports the BIST code
• Multi-block options for the best aspect ratio
• View Details