UMC Free Library - 0.15 µm IPs

Faraday's 0.15µm cell library products derive their optimized driving strength from Faraday's rich experience of over 1500 successful ASIC projects. The extensive library database is easy to use and manage. It enables users to achieve their design goals with ultimate speed, power, and density.

Please check features listed below:

	UMC 0.15µm Process
	UMC L150 Standard Performance Library
	FSB0G_A Generic Core Cells FSB0G_A Generic I/O Cells FSB0G_A_T33_PCIX_IO FSB0G_A_TMVH33L25_SSTL2C2WLVTTL_IO FSB0G_A_T33_LVPECL_IO FSB0G_A_SH (1Port SRAM) FSB0G_A_SJ (Dual Port SRAM) FSB0G_A_SY (1 Port Register File) FSB0G_A_SZ (2 Port Register File) FSB0G_A_SP (VIA ROM) FXPLL010HB0G_APGD FXDLL311HB0G FZOTG110HB0G

	UMC L150 Standard Performance Features
	FSB0G_A Generic Core Cells
	UMC's 0.15μm 1.5V/3.3V Logic Standard Performance Process Raw gate density: 150,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Support arithmetic cells for data-path designs. Full set of gated clock buffers for power saving Only Metal 1 used in layout, each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FSB0G_A Generic I/O Cells
	UMC's 0.18μm 1.8V/3.3V Low Leakage Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSB0G A_T33_GENERIC_IO UMC's 0.15μm 1.5V/3.3V Logic Standard Performance Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSB0G A_50VT_GENERIC_IO

	FSB0G_A_T33_PCIX_IO
	UMC's 0.15μm 1.5V/3.3V Logic Standard Performance Process Support PCI33, PCI66, PCIX 133MHz 3.3V input, 3.3V output drive Input buffer with programmable pull up resistance, pull down resistance, Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSB0G_A_TMVH33L25_SSTL2C2WLVTTL_IO
	UMC's 0.15μm 1.5V/3.3V Logic Standard Performance Process 3.3V LVTTL input, 3.3V LVTTL output drive 2.5V SSTL2 input, 2.5V SSTL2 output drive Output buffer with SSTL2 (Class II) / LVTTL (20mA) driving strength Input buffer with Schmitt trigger in LVTTL mode, power down function in SSTL2 mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSB0G_A_T33_LVPECL_IO
	UMC's 0.15μm 1.5V/3.3V Standard Performance Logic Process 3.3V PECL I/O cells Options for 25 ohms and 50 ohms output buffers 300MHz for differential type drivers and receivers 250MHz for single-ended type driver and receivers Support power down mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSB0G_A_SH (1Port SRAM)
	Operating voltage range: 1.35V ~ 1.65V Operating junction temp. range : -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSB0G_A_SJ (Dual Port SRAM)
	Operating voltage range: 1.35V ~ 1.65V Operating junction temp. range : -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Standard performance device-based design Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write and word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column MUX options for the best aspect ratio View Details

	FSB0G_A_SY (1 Port Register File)
	Operating voltage range: 1.35V ~ 1.65V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM with CK rising edge Clocked WEB input pins to RAM at CK rising edge : Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSB0G_A_SZ (2 Port Register File)
	Operating voltage range: 1.35V ~ 1.65V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B)rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSB0G_A_SP (VIA ROM)
	Operating voltage range: 1.35V ~ 1.65V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read operation Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at CK rising edge VIA2 layer programmable codes Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout generator Memory compiler preview UI (Memaker) BIST circuitry supported Multi-block options for the best aspect ratio View Details

	FXPLL010HB0G_APGD
	UMC 0.15μm 1.5V Standard Process (SP) Operating voltage range : 1.35V~1.65V Operating junction temperature : -40℃ ~ 125℃ IP's minimum metal requirement : 3 metal layers Output frequency range : 20~300MHz 6-bit programmable pre-divider 6-bit programmable loop divider Power-down mode Built-in loop filter Built-in ESD protection circuit＞2KV (HBM) Built-in core limited power / ground cell View Details

	FXDLL311HB0G
	UMC 0.15μm 1.5V standard performance process Operating voltage range: 1.35V ~ 1.65V Operating junction temperature range: -40 ~ ℃125℃ IP's minimum metal requirement: 4 metal layers Input clock frequency range: 100MHz ~ 200MHz DDR SDRAM controller usage Four channels with 20% DQS delay Low jitter output Power-down mode No external component required View Details

	FZOTG110HB0G
	UMC 0.15 μm L150 / SP 3.3V/1.5V logic process 3.3V power supply (I/O) with 5V tolerance Compliant with USB specification 1.1 Compliant with USB On-The-Go supplement specification 1.0 (ECN. Specification) Built-in pull-up / pull-down resistors Support full speed data transfer rate of 12 Mbps Support low speed data transfer rate of 1.5 Mbps ESD protection > 3KV (HBM) IP's minimum metal requirement: 5 metal layers (5M) View Details