UMC Free Library - 0.18 µm IPs

Faraday's 0.18µm library products' optimized cell driving strength is based on Faraday's rich experience of over 1,500 successful ASIC projects. It provides an extensive library database that is easy to manage and easy to use. By using the most up-to-date synthesis tools, users can shorten the design time and achieve their design goal more effectively.

Please check features listed below:

	UMC 0.18µm Process
	UMC L180 Generic II Library
	FSA0A_C Generic Core Cells FSA0A_C Generic I/O Cells FSA0A_C_T18_OSC_IO FSA0A_C_T33_PCIX_IO FSA0A_C_TMVH33L25_S0STL2C2WLVTTL_IO FSA0A_C_T33_LVPECL_IO FSA0A_C_T33_ANALOGESD_IO FSA0A_C_SU (1 Port SRAM) FSA0A_C_SJ (Dual Port SRAM) FSA0A_C_SY (1 Port Register File) FSA0A_C_SZ (2 Port Register File) FSA0A_C_SP (VIA ROM) FXPLL031HA0A_APGD FXDLL311HA0A FZOTG110HA0A FXLVRX080HA0A FXLVTX080HA0A

	UMC L180 Low Leakage Library
	FSA0L_A Generic Core Cells FSA0L_A Generic I/O Cells FSA0L_A_T33_ANALOGESD_IO FSA0L A_T33_OSC_IO FSA0L_A_SH (1Port SRAM) FSA0L_A_SJ (Dual Port SRAM) FSA0L_A_SY (1 Port Register File) FSA0L_A_SZ (2 Port Register File) FSA0L_A_SP (VIA ROM) FXPLL010HA0L_APGD

	UMC L180 High Voltage Process
	FSA0V_A_Generic_Core FSA0V_A_T18_Generic_CD_IO FSA0V_A_SU (1Port SRAM) FSA0V_A _SJ (Dual Port SRAM)

	UMC L180 RFMM Process
	FSA0M_A_GENERIC_CORE FSA0M_A_T33_GENERIC_IO FSA0M_A_50VT_GENERIC_IO FSA0M_A_SU FSA0M_A_SJ

	UMC L180 CMOS Image Sensor Process
	FSA0I_A_GENERIC_CORE FSA0I_R_GENERIC_CORE FOA0I_A33_T33_GENERIC_IO FOA0I_A33_50VT_GENERIC_IO FOA0I_R33_T33_GENERIC_IO FSA0I_A_SL

	UMC L180 Generic II Features
	FSA0A_C Generic Core Cells
	UMC’s 0.18μm 1.8V Generic II Logic Process Raw gate density: 110,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Support arithmetic cells for data-path designs Full set of gated clock buffers for power saving Only Metal 1 used in layout, each cell has at least one sub/ well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FSA0A_C Generic I/O Cells
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSA0A_C_T33_GENERIC_IO UMC's 0.18μm 1.8V/3.3V Generic II Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FSA0A_C_50VT_GENERIC_IO

	FSA0A_C_T18_OSC_IO
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process High frequency oscillator pad range : 1MHz ~ 66MHz Low frequency oscillator pad range : 32KHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: (only "High" provided in AIP Free Lib)

	FSA0A_C_T33_PCIX_IO
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process Support PCI33, PCI66, PCIX 133MHz 3.3V input, 3.3V output drive Input buffer with programmable pull up resistance, pull down resistance, Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSA0A_C_TMVH33L25_SSTL2C2WLVTTL_IO
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process 3.3V LVTTL input, 3.3V LVTTL output drive 2.5V SSTL2 input, 2.5V SSTL2 output drive Output buffer with SSTL2 (Class II) / LVTTL (20mA) driving strength Input buffer with Schmitt trigger in LVTTL mode, power down function in SSTL2 mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSA0A_C_T33_LVPECL_IO
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process 3.3V PECL I/O cells Options for 25 ohms and 50 ohms output buffers 300MHz for differential type drivers and receivers 250MHz for single-ended type driver and receivers Support power down mode Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details

	FSA0A_C_T33_ANALOGESD_IO
	UMC's 0.18μm 1.8V/3.3V Generic II Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details

	FSA0A_C_SU (1 Port SRAM)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operation One read / write port High density, fully customized layout density High speed – 350 MHz (4K x 16, worst case) Automatic power down to eliminate operating current Clocked address inputs and CS into RAM with CK rising edge Clocked WEB inputs into RAM with CK rising edge Clocked DI inputs into RAM with CK rising edge Byte write and word write operations available Different aspect ratios to best fit chip floor plan Variable capacity: maximum 512K bits Tri-state output buffer View Details

	FSA0A_C_SJ (Dual Port SRAM)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) BIST circuit supported Multi-block options for the best aspect ratio View Details

	FSA0A_C_SY (1 Port Register File)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operation Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSA0A_C_SZ (2 Port Register File)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FSA0A_C_SP (VIA ROM)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operation Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at CK rising edge Via-1 layer programmable codes Memory compiler preview UI (Memaker) BIST circuitry supported Multi-block options for the best aspect ratio View Details

	FXPLL031HA0A_APGD
	UMC 0.18μm 1.8V 1P8M Logic process Operating voltage range: 1.62V ~ 1.98V Operating junction temperature range: -40 ~ 125℃ IP's minimum metal requirement: 3 metal layers Power-down mode No external component required FREFX input frequency range: 5MHz~100MHz CKOUT output frequency range: 20MHz~300MHz Built-in PLL testing circuit Built-in ESD protection circuit Built-in Power/Ground pad View Details

	FXDLL311HA0A
	UMC 0.18μm 1.8V 1P8M Logic process Operating voltage range: 1.62V ~ 1.98V Operating junction temperature range: -40℃ ~ 125℃ IP's minimum metal requirement: 3 metal layers DDR SDRAM controller usage Four channels with 20% DQS delay Low jitter output Power-down mode No external component required FREF input frequency range:100MHz~200MHz CKOUT output frequency range:100MHz~200MHz View Details

	FZOTG110HA0A
	UMC 0.18μm 1.8V / 3.3V Generic II logic process 3.3V power supply (I/O) with 5V tolerance Compliant with USB specification 1.0 and 1.1 Compliant with USB On-The-Go supplemental specification 1.0 (ECN.Spec.) Built-in pull-up / pull-down resistors Support full speed data transfer rate, 12Mbps Support low speed data transfer rate,1.5Mbps ESD protection > 2KV (HBM) IP’s minimum metal requirement: 4 metal layers (4M) IP’s minimum oxide requirement: dual oxide (2G) View Details

	FXLVRX080HA0A
	UMC 0.18 μm 1.8V/3.3V 1P4M logic process Operating voltage range: 3.0V ~ 3.6V Operating junction temp. range: 0℃ ~ 115℃ Recommended operating ambient temp. range: 0℃ ~ 85℃ Support 20 to 85 MHz shift clock 4:28 data channel expansion at a throughput of up to 297.5 Mb/s Support VGA, SVGA, XGA and single pixel SXGA PLL requires no external components Power-down mode supply current < 1 mA Compatible with TIA / EIA-644 LVDS standard Support open, short and terminated input fail-safe Skew margin: ± 400 ps at 65 MHz Operating frequency: 20 ~ 85 MHz View Details

	FXLVTX080HA0A
	UMC 0.18 μm 1.8V/3.3V 1P4M logic process Operating voltage range: 3.0V ~ 3.6V Operating junction temp. range: 0℃ ~ 115℃ Recommended operating ambient temp. range: 0℃ ~ 85℃ Support 20 to 85 MHz shift clock 28:4 data channel compression at a throughput of up to 297.5 Mb/s Support VGA, SVGA, XGA and single pixel SXGA PLL requires no external components Power-down mode supply current < 1 mA Compatible with TIA / EIA-644 LVDS standard Operating frequency: 20 ~ 85 MHz View Details

	UMC L180 Low Leakage Features
	FSA0L_A Generic Core Cells
	UMC’s 0.18μm 1.8V/3.3V 1P6M Logic Low Leakage Process Raw gate density: 110,000 gates/mm2 offers high density needed for low cost applications Complete set of models for industry-standard EDA tools Support arithmetic cells for data-path designs Gated clock buffers for power saving Flexible row abutment Support cells of various driving strengths Build-in antenna diode for all I/O cells and parts of core cells All Flip-Flops have corresponding scan cell Rich set of AOI/AO/OAI/OA complex cells View Details

	FSA0L_A Generic I/O Cells
	UMC's 0.18μm 1.8V/3.3VLow Leakage Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSA0L_A_T33_GENERIC_IO UMC's 0.18μm 1.8V/3.3V Low Leakage Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FSA0L_A_50VT_GENERIC_IO

	FSA0L_A_T33_ANALOGESD_IO
	UMC's 0.18μm 1.8V/3.3V Low Leakage Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details

	FSA0L_A_T33_OSC_IO
	UMC's 0.18μm 1.8V/3.3V low leakage logic process High frequency oscillator pad range : 1MHz ~ 66MHz Low frequency oscillator pad range : 32kHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in antenna diodes for all input pins from core Dedicated power and ground for noise immunity ESD robustness and latch-up immunity proven by silicon View Details: (only "High" provided in AIP Free Lib)

	FSA0L_A_SH (1Port SRAM)
	Operating voltage range: 1.62V ~ 1.98V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density per customer configuration Automatic power down mechanism to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write and word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Multi-block options for the best aspect ratio View Details

	FSA0L_A_SJ (Dual Port SRAM)
	Operating voltage range:1.62V ~ 1.98V Operating junction temp. range: -40℃ ~ 125℃ Recommended operating ambient temp. range:0℃ ~ 85℃ Synchronous read and write operations Fully customized layout density Minimum metal requirement:5 metal layers Automatic power down to eliminate DC current Clocked address inputs and CSA (B) to RAM with CKA (B) rising edge Clocked WEA (B) N input pins to RAM with CKA (B) rising edge Clocked DIA (B) input pins to RAM with CKA (B) rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST circuit supported Multi-block options for the best aspect ratio View Details

	FSA0L_A_SY (1 Port Register File)
	Operating voltage range:1.62V ~ 1.98V Operating junction temp. range: -40℃ ~ 125℃ Recommended operating ambient temp. range:0℃ ~ 85℃ Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Memory compiler preview UI (memaker) BIST circuitry supported Column mux options for the best aspect ratio View Details

	FSA0L_A_SP (VIA ROM)
	Operating voltage range:1.62V ~ 1.98V Operating junction temp. range: -40℃ ~ 125℃ Recommended operating ambient temp. range:0℃ ~ 85℃ Minimum metal requirement:4 metal layers Synchronous read and write operations Fully customized layout density per customer configuration Programming using VIA1 Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at CK rising edge Memory compiler preview UI (Memaker) BIST circuit supported Multi-block options for the best aspect ratio View Details

	FXPLL010HA0L_APGD
	UMC 0.18μm 1.8V low leakage process Operating voltage range: 1.62V ~ 1.98V Input frequency range: 1 ~ 100 MHz Output frequency range: 12.5 ~ 200 MHz 8-bit programmable pre-divider 8-bit programmable loop-divider IP’s minimum metal requirement: 3 metal layers Power-down mode Built-in loop filter Built-in ESD protection circuit > 2KV(HBM) Built-in core limited Power/Ground cell Built-in test mode PLL-Lock signal provided View Details

	UMC L180 High Voltage Process
	FSA0V_A_Generic_Core
	Raw gate density: 110,000 gates/mm2, offering high density needed for low cost applications Complete set of models for industry-standard EDA tools Supports arithmetic cells for data-path designs Gated clock buffers for power saving Flexible row abutment Supports cells of various driving strengths Built-in antenna diode for all I/O cells and part of core cells All flip-flops have corresponding scan cells Rich set of AOI/AO/OAI/OA complex cells View Details

	FSA0V_A_T18_Generic_CD_IO
	UMC's 0.18μm 1.8V Embedded High Voltage Process 1.8V input, 1.8V output drive Output buffer with programmable drive strength from 1.5mA to 12mA with 1.5mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in antenna diodes for all pins ESD robustness and Latch-up immunity proven by silicon View Details

	FSA0V_A_SU (1Port SRAM)
	Operating voltage range: 1.62 V ~ 1.98 V Operating junction temp. range: -40 °C ~ 125 °C Recommended operating ambient temp. range: 0 °C ~ 85 °C Minimum metal requirement: 4 layers Synchronous read and write operations Fully customized layout density Automatic power-down mechanism to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write and word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview user interface (Memaker) BIST code supported Multiblock options for the best aspect ratio View Details

	UMC L180 RFMM Features
	FSA0M_A_GENERIC_CORE
	Raw gate density: 110 K gates/mm2, offering the high density needed for the low cost applications Provides a complete set of models for the industry-standard EDA tools Supports the arithmetic cells for the data-path design Provides the gated clock buffers for the power-saving function Supports the flexible row abutment Supports the cells of various drive strengths Provides all flip-flops with the corresponding scan cells Supports a rich set of AOI/AO/OAI/OA complex cells View Details

	FSA0M_A_T33_GENERIC_IO
	UMC 0.18 µm Mixode/RFCMOS process 3.3 V input and output drives Output buffer with the programmable driving strength from 2 mA to 16 mA in steps of 2 mA at the 3.3 V operation. Input buffer with the enabled programmable pull-up resistance, pull-down resistance, keeper, and Schmitt-trigger functions Built-in antenna diodes for all the pins ESD robustness and latch-up immunity proven by silicon View Details

	FSA0M_A_50VT_GENERIC_IO
	UMC 0.18 µm Mixmode/RFCMOS process Supports the 3.3 V with 5V tolerance input and 3.3 V output drives Supports the output buffers with the programmable drive strength from 2 mA to 8 mA in steps of 2 mA, and from 4 mA to 16 mA in steps of 4 mA Supports the input buffers with the enabled programmable pull-up resistance, pull-down resistance, keeper, and Schmitt-trigger features Built-in antenna diodes for all the pins ESD robustness and latch-up immunity proven by silicon View Details

	FSA0M_A_SU
	Operating voltage range: 1.62 V ~ 1.98 V Operating junction temperature range: -40 °C ~ 125 °C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density per customer configuration Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CS to the RAM at the CK rising edge Clocked WEB input pin to the RAM at the CK rising edge Clocked DI input pins to the RAM at the CK rising edge Byte write and word write operations available Verilog/VHDL timing simulation model generator SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST code Multi-block options for the best aspect ratio View Details

	FSA0M_A_SJ
	Synchronous read and write operations Fully customized layout density Available for 1.8 V ± 10% Automatic power down to eliminate the DC current Clocked address inputs and CSA(B) to RAM at the CKA(B) rising edge Clocked WEA(B)N input pins to RAM at the CKA(B) rising edge Clocked DIA(B) input pins to RAM at the CKA(B) rising edge Byte write or word write operations available Verilog/VHDL timing/Simulation model generator SPICE netlist generator GDSII layout database Memaker preview UI BIST code supported Multi-block options of the best aspect ratio View Details

	UMC L180 CMOS Image Sensor Features
	FSA0I_R_GENERIC_CORE
	UMC 0.18 µm CMOS Image Sensor process Raw gate density of 75,000 gates/mm² offers high density needed for the low-cost applications Complete set of models for industry-standard EDA tools Uses only M1 in layout Each cell has at least one subtrate/well contact Flexible row abutment Built-in decoupling capacitance to aid the IR drop of filler cells View Details

	FOA0I_A33_T33_GENERIC_IO
	UMC 0.18 µm CIS (CMOS Image Sensor) process 3.3 V input and 3.3 V output drives Output buffer with programmable driving strength from 2 mA to 16 mA with 2-mA steps at 3.3 V operation. Input buffer with enabled programmable pull-up resistance, pull-down resistance, keeper, and Schmitt-trigger functions Built-in antenna diodes for all pins ESD robustness and latch-up immunity proven by silicon View Details

	FOA0I_A33_50VT_GENERIC_IO
	UMC 0.18 µm CMOS Image Sensor process 3.3 V with 5-V tolerance input and 3.3 V output drive Output buffer with programmable driving strength from 2 mA to 8 mA with 2-mA steps, and from 4 mA to 16 mA with 4-mA steps Input buffer with enabled programmable pull-up resistance, pull-down resistance, keeper, and Schmitt-trigger functions Built-in antenna diodes for all pins ESD robustness and latch-up immunity proven by silicon View Details

	FOA0I_R33_T33_GENERIC_IO
	UMC's 0.18 µm CIS (CMOS Image Sensor) process 3.3 V input/output drives Output buffers with programmable drive strengths from 2 mA to 16 mA in steps of 2 mA, at 3.3 V operation Input buffers with enabled programmable pull-up/pull-down resistance, keeper, and Schmitt-trigger Built-in antenna diodes for all pins ESD robustness and latch-up immunity proven by silicon View Details

	FSA0I_A_SL
	Synchronous read and write operations High density and a small memory design area Fully customized layout density Available at 1.8 V ± 10% Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CSB to RAM at the CK rising edge Clocked DI and WEB input pins to RAM at the CK rising edge Both byte write and word write operations available Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Supports BIST code Column Mux options for the best aspect ratio View Details