UMC Free Library - 0.25 Library

Faraday's 0.25µm library products' optimized cell driving strength is based on Faraday's rich experience of over 1,500 successful ASIC projects. It provides an extensive library database that is easy to manage and easy to use. By using the most up-to-date synthesis tools, users can shorten the design time and achieve their design goal more effectively.

Please check features listed below:

	UMC 0.25µm Logic Process
	UMC L250 Library
	FS90A_C_GENERIC_CORE FS90A_C_Generic_I/O_Cells FS90A_C_T25_OSC_IO FS90A_C_T33_ANALOGESD_IO FS90A_C_SU (I Port SRAM) FS90A_C_SY (1 Port RF) FS90A_C_SZ (2 Port RF) FS90A_C_SP (VIA ROM) PLL9019

	UMC L250 Logic Process Features
	FS90A_C_GENERIC_CORE
	UMC 0.25μm 2.5V Logic Process Raw gate density: 67,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Support arithmetic cells for data-path designs Full set of gated clock buffers for power saving Each cell has at least one sub/ well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	FS90A_C_Generic_I/O_Cells
	UMC's 0.25μm 2.5V/3.3V Logic Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details:FS90A_C_T33_GENERIC_IO UMC's 0.25µm 2.5V/3.3V Logic Process 3.3V with 5V tolerance input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 8mA with 2mA step, 4mA to 16mA with 4mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details: FS90A_C_50VT_GENERIC_IO

	FS90A_C_T25_OSC_IO
	UMC's 0.25μm 2.5V/3.3V logic process High frequency oscillator pad range : 1MHz ~ 66MHz Low frequency oscillator pad range : 32KHz ~ 1MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in antenna diodes for all input pins from core Dedicated power and ground for noise immunity ESD robustness and latch-up immunity proven by silicon View Details: (only "High" provided in AIP Free Lib)

	FS90A_C_T33_ANALOGESD_IO
	UMC's 0.25μm 2.5V/3.3V Logic Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details

	FS90A_C_SU (I Port SRAM)
	Operating voltage range: 2.25V ~ 2.75V Operating junction temp. range: 0 °C ~ 115°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operation One (1) read / write port Fully customized layout density High speed - 266 MHz (4K x 16, worst case) Automatic power down mechanism to eliminate DC current Clocked address inputs into RAM with CK rising edge Clocked WEB inputs into RAM with CK rising edge Clocked DI inputs into RAM with CK rising edge Byte write and word write operations available Different aspect ratios to best fit chip floor plan Variable capacity: maximum 512K bits Tri-state output buffer View Details

	FS90A_C_SY (1 Port RF)
	Operating voltage range: 2.25V ~ 2.75V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operation Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM at CK rising edge Clocked WEB input pin to RAM at CK rising edge Clocked DI input pins to RAM at CK rising edge Byte write or word write operations available Memory compiler preview UI (Memaker) BIST code supported Column mux options for the best aspect ratio View Details

	FS90A_C_SZ (2 Port RF)
	Operating voltage range: 2.25V ~ 2.75V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 4 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details

	FS90A_C_SP (VIA ROM)
	Operating voltage range: 2.25 ~ 2.75 V Operating junction temp. range: -40 ~ 125 °C Recommended operating ambient temp. range: 0 ~ 85 °C Minimum metal requirement: 5 metal layers Synchronous read operation Fully customized layout density Automatic power down to eliminate DC current Clocks address inputs and CS to ROM at CK rising edge VIA-1 layer programmable codes Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Multi-block options for the best aspect ratio View Details

	PLL9019
	UMC 0.25μm 2.5V logic process Operating voltage range: 2.25V ~ 2.75V Operating junction temperature range: 0℃ ~ 125℃ IP's minimum metal requirement: 3 metal layers Input frequency range: 5MHz ~ 100MHz Output frequency range: 20MHz ~ 270 MHz Low jitter clock output 2.5V single power source 7-bit programmable pre-divider 7-bit programmable loop divider Built-in isolated PLL testing circuit Power-down mode Bypass mode Built-in loop filter View Details