UMC Free Library - 90 nm IPs

UMC 65 nm Process

	UMC L65 Standard Performance Low-K Library
	FSE0A_A_SH (1 Port SRAM) FSE0A_A_SJ (Dual Port SRAM) FSE0A_A_SY (1 Port Register File) FSE0A_A_SZ (2 Port Register File) FSE0A_A_SP (VIA ROM)

	UMC L65 Low Leakage Low-K Library
	FSE0K_A_SH (1 Port SRAM) FSE0K_A_SJ (Dual Port SRAM) FSE0K_A_SY (1 Port Register File) FSE0K_A_SZ (2 Port Register File) FSE0K_A_SP (VIA ROM) FXPLL030HE0K

	UMC L65 Standard Performance Low-K Library Features

	UMC L65 Low Leakage Low-K Library Features
	FSE0K_A_SH (1 Port SRAM)
	Synchronous read and write operations Low leakage and AC powers High density available at 1.2 V ± 10% Supports one pair of redundant row for the repair function Automatic power-down mechanism to eliminate the DC current Clocked address inputs, CSB, WEB, and DI to RAM at the CK rising edge Supports byte write and word write operations Verilog/VHDL timing simulation model generator PICE netlist generator GDSII layout generator Memaker preview UI Supports the BIST code Column MUX options for the best aspect ratio and speed selection View Details


	FSE0K_A_SJ (Dual Port SRAM)
	Synchronous read and write operations Low leakage device-based design Fully-customized layout density Available at 1.2 V ± 10% Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CSA(B)N to the RAM at the CKA(B) rising edge Clocked WEA(B)N input pins to the RAM at the CKA(B) rising edge Clocked DIA(B) input pins to the RAM at the CKA(B) rising edge Supports byte write and word write operations Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST code Column Mux options for the best aspect ratio Minimum metal requirement: 6 metal layers View Details


	FSE0K_A_SY (1 Port Register File)
	Operating voltage range: 1.08 V ~ 1.32 V Operating junction temperature range: -40 °C ~ 125 °C Recommended Ambient temperature range: 0 °C ~ 85 °C Minimum metal requirement: 6 metal layers Supports synchronous read and write operations Fully-customized layout density Available at 1.2 V ± 10% Automatic power-down mechanism to eliminate DC current Clocked address inputs and CSB to RAM at the CK rising edge Clocked WEB input pin to RAM at the CK rising edge Clocked DI input pins to RAM at the CK rising edge Byte write or word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memaker preview UI Supports the BIST code Column Mux options for the best aspect ratio View Details


	FSE0K_A_SZ (2 Port Register File)
	Synchronous read and write operations Fully-customized layout density Available at 1.2 V ± 10% Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CSA(B)N to RAM at the CKA(B) rising edge Clocked WEB input pins to RAM at the CKB rising edge Clocked DI input pins to RAM at the CKB rising edge Supports the byte write and word write operations Verilog/VHDL timing simulation model generator SPICE netlist generator GDSII layout database Memaker preview UI Column MUX options for the best aspect ratio View Details


	FSE0K_A_SP (VIA ROM)
	Synchronous read operation Fully customized layout density per customer’s configurations Programmable Via1 code High density available at 1.2 V ±10% Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CS to ROM at the CK rising edge Verilog/VHDL timing simulation model generator SPICE netlist generator GDSII layout database Mameker preview UI Supports BIST code Multi-block options for the best aspect ratio View Details