UMC Free Library - 90 nm IPs

To satisfy the power, performance, and integration requirements of complex System-on-a-Chip (SoC) designs, Faraday and UMC are developing a comprehensive set of IP elements optimized for UMC's 90nm process.

The following features and benefits of Faraday's newly released standard performance library provide each customer with the ability to select the cells that will provide their design with the ultimate speed, power, and density.

	UMC L90 Standard Performance Low-K Library
	UMC L90 Standard Performance Low-K Library (RVT) UMC L90 Standard Performance Low-K Library (LVT) UMC L90 Standard Performance Low-K Library (HVT)

	UMC L90 Low Leakage Low-K Library
	UMC L90 Low Leakage Low-K Library (RVT) UMC L90 Low Leakage Low-K Library (LVT) UMC L90 Low Leakage Low-K Library (HVT)

	UMC L90 Standard Performance Low-K Library (RVT)
	FSD0A_A_Generic_Core
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K SP Process Raw gate density: 400,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Full set of gated clock buffers for power saving Only Metal 1 used in layout,each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details


	FOD0A_A_Generic_I/O_Cells
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K SP Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details


	FOD0A_A25_T25_OSC_HIGH_IO
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K SP Process High frequency oscillator pad range: 2MHz ~ 66MHz Programmable output driving capability Oscillation mode / power down (stop) mode / tri-state mode / parallel model Internal feedback resistance Built-in antenna diodes for all pins ESD robustness and Latch-up immunity proven by silicon View Details


	FOD0A_A33_T33_ANALOGESD_IO
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K SP Process 3.3V ESD protection cells for analog I/O 3.3V Power / Ground cells with ESD protection Power-cut cells with ESD protection to separate 3.3V analog blocks from digital ESD robustness and Latch-up immunity proven by silicon View Details


	FSD0A_A_SH (1Port SRAM)
	Synchronous read and write operations Customized layout density per customer configuration High density available for 1.0 V ±10% Automatic power down to eliminate DC current Clocked address inputs and CS to RAM at the CK rising edge Clocked WEB input pin to RAM at the CK rising edge Clocked DI input pins to RAM at the CK rising edge Byte write and word write operations available Verilog/VHDL timing and simulation model generator SPICE netlist generator GDSII layout generator Memory compiler preview UI (Memaker) Support BIST code Column multiplex options for the best aspect ratio and speed selection View Details

	FSD0A_A_SJ (Dual Port SRAM)
	Operating voltage range: 0.9V ~ 1.1V Operating junction temp. range : -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 5 metal layers Synchronous read and write operations Standard performance device-based design Fully customized layout density Automatic power down mechanism to eliminate DC current Clocked address inputs and CSA(B) to RAM with CKA(B) rising edge Clocked WEA(B)N input pins to RAM with CKA(B) rising edge Clocked DIA(B) input pins to RAM with CKA(B) rising edge Byte write and word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column MUX options for the best aspect ratio View Details


	FSD0A_A_SY (1 Port Register File)
	Operating voltage range: 0.9 ~ 1.1 V Operating junction temp. range: -40 ~ 125 °C Recommended operating ambient temp. range: 0 ~ 85 °C Minimum metal requirement: 6 metal layers Synchronous read and write operations Fully customized layout density Available for 1 V ± 10 % Automatic power down to eliminate DC current Clocked address inputs and CSB to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog/VHDL timing/simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Column mux options for the best aspect ratio View Details


	FSD0A_A_SZ (2 Port Register File)
	Operating voltage range: 0.90V ~ 1.10V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read and write operations Fully customized layout density Automatic power down to eliminate DC current Clocked address inputs and CSA(B)N to RAM with CKA(B) rising edge Clocked WEB input pins to RAM with CKB rising edge Clocked DI input pins to RAM with CKB rising edge Byte write or word write operations available Verilog / VHDL timing /simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) Column mux options for the best aspect ratio View Details


	FSD0A_A_SP (VIA ROM)
	Operating voltage range: 0.9V ~ 1.1V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read operation Fully customized layout density per customer request Programming code by VIA1 High density, available for 1.0V ± 10% Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at CK rising edge Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Multi-block options View Details


	FXPLL110HD0A
	UMC 90 nm 1V standard logic process Operating voltage range: 0.9 V ~ 1.1 V Operating junction temperature range: -40 °C ~ 125 °C Minimum metal requirement: 8 metal layers Low jitter output Supports power-down and bypass modes Built-in loop filter View Details

	UMC L90 Standard Performance Low-K Library (LVT)
	FSD0T_A_Generic_Core
	UMC 90nm 1P9M Logic/Mixed Mode Low-K LVT SP Process Raw gate density: 400,000 gates/mm2 offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for performance Complete set of models for industry-standard EDA tools Full set of gated clock buffers for power saving Only Metal 1 used in layout, each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details

	UMC L90 Low Leakage Low-K Library (RVT)
	FSD0K_A_Generic_Core
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K LL-RVT Process The 400,000 gates/mm2 raw gate density offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for better performance Complete set of models for industry-standard EDA tools Full set of gated clock buffers for power saving Only Metal 1 is used in layout, each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details


	FOD0K_A33_T33_Generic_IO
	UMC's 90nm 1P9M Logic/Mixed Mode Low-K LL-RVT Process 3.3V input, 3.3V output drive Output buffer with programmable drive strength from 2mA to 16mA with 2mA step Input buffer with programmable pull up resistance, pull down resistance, keeper, and Schmitt trigger Built-in Antenna diodes for all pins ESD Robustness and Latch-up immunity proven by Silicon View Details


	FOD0K_A_T25_OSC_HIGH_IO
	UMC 90 nm logic LL-RVT (low-K) process High frequency oscillator pad range: 1 MHz ~ 66 MHz Low frequency oscillator pad range: 32 KHz ~ 1 MHz Programmable output driving capability Oscillation/power-down (stop)/tri-state/parallel models Internal feedback resistance Built-in antenna diodes for all the pins Silicon proven ESD robustness and latch-up immunity View Details


	FOD0K_A_T25_OSC_LOW_IO
	UMC 90 nm logic LL-RVT (low-K) process High frequency oscillator pad range: 1 MHz ~ 66 MHz Low frequency oscillator pad range: 32 KHz ~ 1 MHz Programmable output driving capability Oscillation/power-down (stop)/tri-state/parallel models Internal feedback resistance Built-in antenna diodes for all the pins Silicon proven ESD robustness and latch-up immunity View Details


	FSD0K_A_SH (1Port SRAM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range: -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read and write operations Full custom layout density per customer configuration Automatic power down to eliminate DC current Clocked address inputs and CS to RAM with CK rising edge Clocked WEB input pin to RAM with CK rising edge Clocked DI input pins to RAM with CK rising edge Byte write or word write operations available Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout generator Memory compiler preview UI (memaker) BIST code supported Column mux options for the best aspect ratio and speed selection View Details


	FSD0K_A_SJ (Dual Port SRAM)
	Synchronous read and write operations Low leakage device-based design Fully customized layout density Available in 1.2 V ± 10% Automatic power-down mechanism to eliminate the DC current Clocked address inputs and CSA(B) to RAM at the CKA(B) rising edge Clocked WEA(B)N input pins to the RAM at the CKA(B) rising edge Clocked DIA(B) input pins to the RAM at the CKA(B) rising edge Supports byte/word write operations Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview user interface Supports the BIST codes Column Mux options for the best aspect ratio View Details


	FSD0K_A_SY (1 Port Register File)
	Synchronous read and write operations Fully customized layout density 1.2 V ±10% operating voltage available Automatic power down to eliminate the DC current Clocked address inputs and CSB to RAM at the CK rising edge Clocked WEB and DI input pins to RAM at the CK rising edge Byte write and word write operations available Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI BIST code supported Column Mux options for the best aspect ratio View Details


	FSD0K_A_SZ (2 Port Register File)
	Synchronous read and write operations Fully customized layout density Available in 1.2 V ± 10% Automatic power down to eliminate the DC current Clocked address inputs and CSA(B)N to the RAM at the CKA(B) rising edge Clocked WEB input pins to the RAM at the CKB rising edge Clocked DI input pins to the RAM at the CKB rising edge Supports byte write and word write operations Verilog/VHDL timing/simulation model generators SPICE netlist generator GDSII layout database Memaker preview UI Column Mux options for the best aspect ratio View Details


	FSD0K_A_SP (VIA ROM)
	Operating voltage range: 1.08V ~ 1.32V Operating junction temp. range : -40°C ~ 125°C Recommended operating ambient temp. range: 0°C ~ 85°C Minimum metal requirement: 6 metal layers Synchronous read operation Fully customized layout density per customer request Programming code by VIA1 Automatic power down to eliminate DC current Clocked address inputs and CS to ROM at CK rising edge Verilog / VHDL timing / simulation model generator SPICE netlist generator GDSII layout database Memory compiler preview UI (Memaker) BIST code supported Multi-block options for the best aspect ratio View Details

	UMC L90 Low Leakage Low-K Library (LVT)
	FSD0J_A_Generic_Core
	UMC 90nm 1P9M Logic / Mixed Mode Low-K LL-HVT Process The 400,000 gates/mm2 raw gate density offers high density needed for low cost applications Wide drive strength range and optimized P/N ratio for better performance Complete set of models for industry-standard EDA tools Full set of gated clock buffers for power saving Only Metal 1 is used in layout, each cell has at least one sub / well contact Flexible row abutment Built-in decoupling capacitance to aid IR drop in filler cells View Details