Core Cell Library Family
    The development of library is based on Faraday's rich experience of thousands of ASIC successes in market. Consequently, Faraday is able to optimize these cells to achieve better performance, density and power rating.
   


 


Core Cells Features

  • Rich set of AOI/AO/OAI/OA complex cells
  • All Flip-Flops have corresponding scan cell
  • Optimized P/N ratio for performance
  • Complete set of models for industry-standard EDA tools
  • Support Enable Flip-Flop and Gating-Clock Latch for Power Management
  • Built-in capacitor for filler cell
  • Built-in Antenna diode
  • Arithmetic cells for data-path designs 
I/O Cells Features
  • 3.3V CMOS Generic I/O cell and 3.3V LVTTL with 5V tolerance Generic I/O cell
  • Programmable output slew rate
  • Staggered and in-line I/O structure support
  • Stagger and in-line I/O transformation corner
  • Output buffer with programmable drive strengths from 2mA to 8mA by 2mA step and 4mA~16mA by 4mA step
  • Input buffer with programmable pull-up, pull-down, keeper and Schmitt trigger
  • Built-in antenna diode for all input cells
  • Built-in level-shift
  • Support IBIS model
  • ESD robustness and latch-up( >±200mA) immunity proven by silicon
  • -ESD specification:   HBM > ±2kV
    MM > ±200V
    CDM > ±500V

EZIO™ Technology

The EZIO™ is a proprietary technology that empowers all Faraday's I/O cells with easily configurable features such as real time change I/O on "Silicon", match output impedance to transmission line loading, and the elimination of noise. The table below shows 3 examples of EZIO™ applications.